Various software tools are used to support developing and implementing an electronic circuit design. A design entry tool allows a user to specify the functional characteristics of an electronic circuit. Example design entry tools include high-level modeling systems, hardware description languages, and schematic capture. Once the design is specified, a synthesis tool may be applied to the high-level design to generate a netlist. And from the netlist, the design may be simulated or mapped to a particular device or chip technology.
Some designs are targeted for implementation on field programmable gate arrays (FPGAs). FPGAs include lookup tables that are programmable to implement various logic functions. After device mapping, the design data includes initialization values for the LUTs used to implement the design.
The initialization values of LUTs may be useful for debugging designs. For example, when analyzing and adjusting a design for conformance to maximum delay parameters, it may be useful to combine, if feasible, the logic implemented on two LUTs into a single LUT since each LUT has a constant delay. The initialization value of the LUT may indicate whether the capabilities of the LUT are being fully used. If a LUT's capabilities are only partially used, the functions of two or more LUTs may be combined into a single LUT to reduce the maximum delay.
In order to determine whether a LUT is candidate for combining logic functions, the initialization value of the LUT may be examined to determine the extent to which the capabilities of the LUT are utilized. A user may view the initialization value for LUT with certain design tools. However, these tools often output this configuration value in hexadecimal form. The user may thereby be forced to decode the hexadecimal value to determine whether the LUT may be combined with another LUT.
The present invention may address one or more of the above issues.